Agent_IC_design_for_vivado

RTL waveform analysis CLI for debug, CI, and AI agents. Natively reads VCD, FST (preferred — ~10× smaller), and GHW. On linux-amd64, experimental support for WLF and FSDB via each vendor's own reader library. Use when the user has a waveform file (.vcd, .fst, .ghw, .wlf, .fsdb) and wants to inspect, search, compare, or summarize signals — triggers on any mention of waveform analysis, signal queries, RTL debug, simulation results, or VCD/FST/WLF/FSDB files.

VCD waveform analysis for RTL debug. Use when the user has a .vcd file and wants to inspect, search, compare, or summarize digital simulation waveforms. Triggers include any mention of VCD files, waveform analysis, signal dump inspection, RTL debug, simulation results, value change dump, or specific VCD signal queries like "what is the value of X at time Y", "when does valid go high", "compare state at T1 vs T2", "find all AXI handshakes". Also triggers when the user uploads a .vcd file or references one by path. Do NOT use for FSDB, SHM, WLF, or other proprietary waveform formats — those require vendor tools to convert to VCD first.

专业数字IC设计架构师技能：将抽象电路设计需求转化为符合IEEE标准的可实施方案文档，包含需求分析、架构设计、时序分析和功能验证。Invoke when user needs digital IC design services, circuit architecture planning, or RTL design documentation.

专业数字IC设计师技能：将设计文档转化为符合Verilog代码规范的RTL实现，自动生成可综合代码、testbench和验证报告。Invoke when user needs to convert design documentation to RTL code, or needs Verilog implementation following industry standards.

专业数字IC验证师技能：使用UVM和SystemVerilog对RTL设计进行功能验证，严格按照设计文档进行验证，生成验证报告。Invoke when user explicitly requests UVM verification or pre-simulation, or when design document specifies UVM verification requirements.