用 Codex 或 Claude 帮你安装 复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它检查 Skill 页面并帮你完成安装。
直接命令不会经过审查 Prompt;运行前请先检查来源。
npx skills add https://github.com/babyworm/rtl-agent-team --skill syn-tool-profiles命令会保持在同一行。复制前请横向滚动并检查完整内容。
想先保存到本地?可下载 SkillsMP 当前能够提供的文件。
Initialize RTL project workspace: directory structure, coding rules, phase guides. Run once per project. Triggers: 'init project', 'new project'.
Internal reference: rtl p5 verify policy (agent-loaded; do not invoke).
P5 formal verification: SVA proof via SymbiYosys BMC/induction on lint-clean RTL. Triggers 'formal verification', 'prove property', 'SVA'.
正在显示 SKILL.md
| name | syn-tool-profiles |
| description | Internal reference: syn tool profiles (agent-loaded; do not invoke). |
| user-invocable | false |
syn/scripts/run_syn.shtool, status, area, timing_summary, log_path, replay_path--max-cores (default 8) via
set_host_options / set_db max_cpus_per_server. Tools auto-limit to the
licensed/physical maximum, so over-requesting is safe (graceful degradation).sram_sp/tp/dp) keeps its 2-D array under
synopsys translate_off, so DC/Genus skip it. With no compiled macro linked,
run_syn.sh blackboxes the wrapper (set_dont_touch + set_disable_timing) and
WARNs. Select a process with --mem-process and link the macro with --mem-lib
for real timing/area. See the synth-memory-blackbox design spec.syn/
├── db/ — Binary databases (.ddc, .db, .genus_db)
├── vnet/ — Gate-level netlists (.v, .json)
├── svf/ — Setup Verification Flow (.svf, DC only)
├── scr/ — Generated scripts (.tcl, .ys) + replay/
├── rpt/ — Reports (area, timing, power, qor)
├── log/ — Synthesis logs
├── temp/ — Cache and temporary files
└── work/ — Tool work directories
yosys:
syn/scripts/run_syn.sh --tool yosys --top <top> -f rtl/filelist_top.fsyn/scripts/run_syn.sh --tool yosys --top <top> -f rtl/filelist_top.f --liberty <lib>dc_shell:
syn/scripts/run_syn.sh --tool dc_shell --top <top> -f rtl/filelist_top.f--liberty <tech.lib> --sdc <design.sdc> --script <dc.tcl> --max-cores <n>--mem-process <NAME> --mem-lib <macro.db> --mem-module <name> --mem-strict.ddc → syn/db/, netlist → syn/vnet/, .svf → syn/svf/, .synopsys_dc.setup → syn/scr/genus:
syn/scripts/run_syn.sh --tool genus --top <top> -f rtl/filelist_top.f--liberty <tech.lib> --sdc <design.sdc> --script <genus.tcl> --max-cores <n>--mem-process <NAME> --mem-lib <macro.db> --mem-module <name> --mem-strict.genus_db → syn/db/, netlist → syn/vnet/vivado (FPGA):
syn/scripts/run_syn.sh --tool vivado --top <top> --script <vivado.tcl>--script is mandatory: part number, XDC and IP handling are
project-specific, so there is no generic non-project recipe to auto-generate.
The Tcl must carry its own synth_design -top <top> -part <part> flow.-f, --liberty and the --mem-* options do not apply — the Tcl owns source
and constraint loading.The exact binaries and batch switches the runner uses. These are the shapes each vendor documents; changing them silently breaks the stage.
| Tool | Invocation | Why this shape |
|---|---|---|
yosys | yosys -s <ys> | — |
dc_shell | dc_shell -64bit -f <tcl> | Synopsys shells spell the switch -64bit |
genus | genus -batch -files <tcl> | Without -batch Genus keeps an interactive shell alive after sourcing. -64 is an RTL-Compiler-era switch — Genus is 64-bit only and newer releases reject it |
vivado | vivado -mode batch -source <tcl> -nojournal -nolog | Batch mode exits when the script finishes; Tcl mode would return to a prompt. Suppressing the journal/log keeps parallel runs from colliding |
| Tier | Tools | Capabilities | sv2v Handling |
|---|---|---|---|
| 1 (commercial) | dc_shell, genus | Full synthesis + timing + area + PPA | Not needed (native SV support) |
| 2 (oss) | yosys | Latch detection, unmapped cells, basic area estimate | Script handles internally (Layer 2) |
| 3 (none) | — | Synthesis skipped with WARNING | N/A |
Use get_synthesis_tier() from lib/tool-runner.sh to determine tier at runtime.
sv2v Policy: sv2v is a Layer 2 concern — run_syn.sh handles it internally for Yosys.
Agent prompts and policy skills MUST NOT instruct manual sv2v execution.
Canonical source stays SystemVerilog; tool adaptation is the script's responsibility.
--skip-if-unavailable flag: When passed to run_syn.sh, tool absence or license failure
produces WARNING + clean exit (exit 0) instead of hard failure. Use in optional synthesis contexts
(Stream B smoke test, V8 estimation without commercial tools).
FAIL: tool fatal error, netlist generation failure, or unusable reportPASS: synthesis completes and required summary artifacts are generatedSKIPPED: tool not available and --skip-if-unavailable was set (non-blocking)