Initialize RTL project workspace: directory structure, coding rules, phase guides. Run once per project. Triggers: 'init project', 'new project'.
Internal reference: rtl p5 verify policy (agent-loaded; do not invoke).
P5 formal verification: SVA proof via SymbiYosys BMC/induction on lint-clean RTL. Triggers 'formal verification', 'prove property', 'SVA'.
Yosys synthesis estimation on lint-clean RTL — 'synth check', 'area/timing estimate', 'generate SDC'; detects latches, emits DC/Genus-ready SDC.
Internal reference: rtl p5s sva policy (agent-loaded; do not invoke).
systemverilog-assertion project conventions (loaded by writer agents; do not invoke).
Internal reference: rtl p5s uvm policy (agent-loaded; do not invoke).
P5 UVM verification on commercial simulators (VCS/Questa/Xcelium). Use when UVM methodology or constrained-random sequences/scoreboards are mandated.