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codejunkie99
GitHub 创作者资料

codejunkie99

按仓库查看 5 个 GitHub 仓库中的 76 个已收集 skills,并展示近似职业覆盖。

已收集 skills
76
仓库
5
职业领域
4
更新
2026-05-21
仓库浏览

仓库与代表性 skills

#001
prompt-skills
40 个 skills151更新于 2026-04-26
占该创作者 53%
apology-crafter
作家与作者

Use when the user wants to craft a sincere, accountable apology in both written and spoken versions, without deflection. Triggers include "draft an apology", "how should I apologize", "say sorry to".

2026-04-26
difficult-conversation-prep
人力资源专员

Use when the user wants to prepare for a hard conversation with empathetic-but-direct opening, defensiveness handling, and resolution paths. Triggers include "difficult conversation", "hard talk", "tough conversation prep".

2026-04-26
elevator-pitch-builder
作家与作者

Use when the user wants three energy-level variants of an elevator pitch (bold, conversational, data-driven). Triggers include "elevator pitch", "pitch this product", "30 second pitch".

2026-04-26
feedback-giver
人力资源经理综合与运营经理

Use when the user wants to draft spoken feedback using observation/impact/expectation/support framework. Triggers include "give feedback", "feedback to my report", "performance feedback".

2026-04-26
presentation-outliner
作家与作者

Use when the user wants a tight presentation outline with hook, problem, solution, evidence, objection handling, and clear CTA. Triggers include "outline a presentation", "talk outline", "structure my pitch deck".

2026-04-26
data-interpreter
数据科学家

Use when the user wants plain-English interpretation of a dataset including patterns, surprises, and misleading aspects. Triggers include "analyze this data", "interpret these numbers", "what does this data mean".

2026-04-26
research-synthesizer
其他社会科学家及相关工作者

Use when the user has multiple research sources on a topic and wants genuine synthesis of themes, contradictions, and gaps — not separate summaries. Triggers include "synthesize this research", "compare these sources", "research synthesis".

2026-04-26
survey-analyzer
市场调研分析师与营销专员

Use when the user wants to analyze survey results for findings, consensus, division, surprises, and actionable recommendations. Triggers include "analyze survey", "survey results", "what does this survey show".

2026-04-26
当前展示该仓库 Top 8 / 40 个已收集 skills。
#002
Gateflow-Plugin
27 个 skills8611更新于 2026-05-21
占该创作者 36%
gf-tui
软件开发工程师

GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.

2026-05-21
gf-release
软件开发工程师

GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.

2026-05-20
gf-fusesoc
软件开发工程师

FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.

2026-04-15
gf-learn
软件开发工程师

SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.

2026-04-15
gf-router
软件开发工程师

Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.

2026-04-15
gf
计算机硬件工程师

Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital hardware module.

2026-04-15
gf-summary
软件开发工程师

Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.

2026-04-15
gf-architect
建筑师(景观及海军建筑除外)

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"

2026-04-11
当前展示该仓库 Top 8 / 27 个已收集 skills。
#003
gateflow-cli
7 个 skills30更新于 2026-02-05
占该创作者 9.2%
gateflow-behavior
软件开发工程师

This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring explicit commands.

2026-02-05
systemverilog-rtl-design
软件开发工程师

Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register file', 'always_ff', 'always_comb', 'generate', or asks about synthesis-related coding.

2026-02-05
systemverilog-lint-fixing
软件开发工程师

This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal', 'fix warnings', 'Verilator error', 'WIDTHTRUNC', 'BLKSEQ', or asks to 'check my code' or 'find errors'. Provides error-specific fix patterns for SystemVerilog lint issues.

2026-02-05
systemverilog-testbench-patterns
软件质量保证分析师与测试员

This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create test stimulus', 'verify the design', 'add clock generation', or 'write a self-checking test'. Provides testbench templates, clock/reset patterns, and assertion guidance.

2026-02-05
systemverilog-verification
软件质量保证分析师与测试员

Provides verification methodology, SVA assertion patterns, coverage techniques, and testbench templates. Use when the user mentions 'testbench', 'assertion', 'SVA', 'property', 'sequence', 'coverage', 'covergroup', 'coverpoint', 'bins', 'cross coverage', 'constrained random', 'randomize', 'constraint', 'simulate', 'waveform', 'VCD', '$display', '$finish', or 'self-checking'.

2026-02-05
vcd-waveform-analysis
软件开发工程师

This skill should be used when the user mentions 'waveform', 'VCD file', 'simulation results', 'signal trace', 'debug the output', 'what happened in sim', 'show me the waves', or 'analyze timing'. Provides VCD parsing, clock detection, anomaly identification, and signal tracing techniques.

2026-02-05
systemverilog-development
软件开发工程师

This skill should be used when the user asks to 'design a module', 'write SystemVerilog', 'implement an FSM', 'create a pipeline', or works with .sv/.svh/.v/.vh files. Provides modern SV conventions, coding patterns, and synthesizability guidance.

2026-02-05
#005
avids-essential-skills
1 个 skills31更新于 2026-04-06
占该创作者 1.3%
已展示 5 / 5 个仓库
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