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codejunkie99
GitHub 创作者资料

codejunkie99

按仓库查看 11 个 GitHub 仓库中的 97 个已收集 skills。

已收集 skills
97
仓库
11
更新
2026年8月18日
这里展示前 8 个仓库;完整仓库列表在下方继续。
仓库浏览

仓库与代表性 skills

apology-crafter
作家与作者

Use when the user wants to craft a sincere, accountable apology in both written and spoken versions, without deflection. Triggers include "draft an apology", "how should I apologize", "say sorry to".

2026年4月26日
difficult-conversation-prep
人力资源专员

Use when the user wants to prepare for a hard conversation with empathetic-but-direct opening, defensiveness handling, and resolution paths. Triggers include "difficult conversation", "hard talk", "tough conversation prep".

2026年4月26日
elevator-pitch-builder
作家与作者

Use when the user wants three energy-level variants of an elevator pitch (bold, conversational, data-driven). Triggers include "elevator pitch", "pitch this product", "30 second pitch".

2026年4月26日
feedback-giver
人力资源经理综合与运营经理

Use when the user wants to draft spoken feedback using observation/impact/expectation/support framework. Triggers include "give feedback", "feedback to my report", "performance feedback".

2026年4月26日
presentation-outliner
作家与作者

Use when the user wants a tight presentation outline with hook, problem, solution, evidence, objection handling, and clear CTA. Triggers include "outline a presentation", "talk outline", "structure my pitch deck".

2026年4月26日
data-interpreter
数据科学家

Use when the user wants plain-English interpretation of a dataset including patterns, surprises, and misleading aspects. Triggers include "analyze this data", "interpret these numbers", "what does this data mean".

2026年4月26日
research-synthesizer
其他社会科学家及相关工作者

Use when the user has multiple research sources on a topic and wants genuine synthesis of themes, contradictions, and gaps — not separate summaries. Triggers include "synthesize this research", "compare these sources", "research synthesis".

2026年4月26日
survey-analyzer
市场调研分析师与营销专员

Use when the user wants to analyze survey results for findings, consensus, division, surprises, and actionable recommendations. Triggers include "analyze survey", "survey results", "what does this survey show".

2026年4月26日
已展示 8 / 40 个已收集 Skill。
gf-tui
软件开发工程师

GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.

2026年5月21日
gf-release
软件开发工程师

GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.

2026年5月20日
gf-fusesoc
电子工程师(非计算机)

FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL…

2026年4月15日
gf-learn
其他高等院校教师

SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.

2026年4月15日
gf-router
电子工程师(非计算机)

Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.

2026年4月15日
gf
电子工程师(非计算机)

Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital…

2026年4月15日
gf-summary
电子工程师(非计算机)

Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.

2026年4月15日
gf-architect
电子工程师(非计算机)

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase",…

2026年4月11日
已展示 8 / 27 个已收集 Skill。
gateflow-behavior
软件开发工程师

This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring…

2026年2月5日
systemverilog-rtl-design
软件开发工程师

Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register…

2026年2月5日
systemverilog-lint-fixing
软件开发工程师

This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal', 'fix warnings', 'Verilator error', 'WIDTHTRUNC', 'BLKSEQ', or asks to 'check my code' or 'find errors'. Provides error-specific fix patterns…

2026年2月5日
systemverilog-testbench-patterns
软件质量保证分析师与测试员

This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create test stimulus', 'verify the design', 'add clock generation', or 'write a self-checking test'. Provides testbench templates, clock/reset…

2026年2月5日
systemverilog-verification
软件质量保证分析师与测试员

Provides verification methodology, SVA assertion patterns, coverage techniques, and testbench templates. Use when the user mentions 'testbench', 'assertion', 'SVA', 'property', 'sequence', 'coverage', 'covergroup', 'coverpoint', 'bins', 'cross coverage',…

2026年2月5日
vcd-waveform-analysis
软件开发工程师

This skill should be used when the user mentions 'waveform', 'VCD file', 'simulation results', 'signal trace', 'debug the output', 'what happened in sim', 'show me the waves', or 'analyze timing'. Provides VCD parsing, clock detection, anomaly identification,…

2026年2月5日
systemverilog-development
软件开发工程师

This skill should be used when the user asks to 'design a module', 'write SystemVerilog', 'implement an FSM', 'create a pipeline', or works with .sv/.svh/.v/.vh files. Provides modern SV conventions, coding patterns, and synthesizability guidance.

2026年2月5日
已展示 11 / 11 个仓库
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