gateflow-behavior

This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring explicit commands.

跳到安装查看文件

仓库: codejunkie99/gateflow-cli
最近来源活动: 2026年2月5日 21:22
检测到的 SKILL.md 语言: 英语
星标: 3
Forks: 0

安装方式

默认使用会先检查来源的 Prompt；你也可以切换为直接命令，或下载本地副本。

用 AI 助手安装

复制这段 Prompt，发给你正在使用的 AI 助手。

Follow https://skillsmp.com/skill-install/prompt.md to install only the Agent Skill at https://github.com/codejunkie99/gateflow-cli/tree/main/packages/claude-plugin/skills/gateflow-behavior.

直接命令不会经过审查 Prompt；运行前请先检查来源。

npx skills add https://github.com/codejunkie99/gateflow-cli --skill gateflow-behavior

命令会保持在同一行。复制前请横向滚动并检查完整内容。

想先保存到本地？可下载 SkillsMP 当前能够提供的文件。

检查来源文件

决定是否安装前，请先阅读 SKILL.md，以及 SkillsMP 当前展示的配套文件。

SKILL.md

来源说明 · 只读预览

name: GateFlow Behavior
description: This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring explicit commands.
version: 2.0.0

# GateFlow Behavior Rules for seamless SystemVerilog development. Claude routes to the right tools automatically — users just describe what they want. ## Smart Chaining When the user's intent spans multiple steps, chain them automatically: - "does it work?" → lint → simulate → analyze VCD → report - "create and test a counter" → generate module → generate testbench → simulate → report - "fix and re-run" → apply fixes → re-simulate → compare results - "is this synthesizable?" → lint with synthesis flags → report issues - "full verification" → simulate → coverage → report gaps → suggest assertions ## Context Awareness - If user just generated a module, "test it" means write a testbench for THAT module - If user just ran simulation, "what happened?" means analyze the VCD - If user just saw lint errors, "fix it" means fix THOSE errors - If user says "again" or "re-run", repeat the last action - If user says "all of them", apply to all files in project ## Behavioral Rules 1. **Just do it** — never ask "do you want to...?" when the intent is clear 2. **Never mention commands** — never say "you can use /gf-lint" or "run /gf-scan" 3. **Chain operations** — "lint and fix" does both without pausing 4. **Be brief** — show results, not explanations of what you're about to do 5. **Remember context** — track what file/module the user is working on 6. **Suggest next step** — after lint, suggest fix; after fix, suggest sim; after sim, suggest waves 7. **Fail forward** — if simulation fails, automatically analyze why

在 GitHub 查看

返回搜索返回安装

systemverilog-rtl-design

Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register file', 'always_ff', 'always_comb', 'generate', or asks about synthesis-related coding.

2026-02-05

systemverilog-lint-fixing

This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal', 'fix warnings', 'Verilator error', 'WIDTHTRUNC', 'BLKSEQ', or asks to 'check my code' or 'find errors'. Provides error-specific fix patterns for SystemVerilog lint issues.

2026-02-05

systemverilog-testbench-patterns

This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create test stimulus', 'verify the design', 'add clock generation', or 'write a self-checking test'. Provides testbench templates, clock/reset patterns, and assertion guidance.

2026-02-05

查看这个仓库的全部 Skills

gateflow-behavior

来源信息

安装方式

用 AI 助手安装

检查来源文件

同仓库更多 Skills

用 AI 助手安装

同仓库更多 Skills