菜单
Create, configure, generate, and upgrade Xilinx IP cores. Use when instantiating IP catalog cores, configuring AXI interconnects, generating IP targets, handling OOC synthesis, upgrading stale IPs, or building block designs.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
| name | vivado-ip |
| version | 1.0.0 |
| description | Create, configure, generate, and upgrade Xilinx IP cores. Use when instantiating IP catalog cores, configuring AXI interconnects, generating IP targets, handling OOC synthesis, upgrading stale IPs, or building block designs. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"📦"}} |
create_ip -name <core_name> -vendor xilinx.com -library ip -module_name <inst_name>
set_property CONFIG.PARAM_NAME <value> [get_ips <inst_name>]
generate_target all [get_ips <inst_name>]
foreach ip [get_ips] {
set status [get_property IP_INTEGRATION_STATUS $ip]
set locked [get_property IS_LOCKED $ip]
puts "IP: $ip | Status: $status | Locked: $locked"
}
report_ip_status -file /tmp/vivaclaw_rpt/ip_status.rpt
upgrade_ip [get_ips -filter {UPGRADE_AVAILABLE == 1}]
create_bd_design "system"
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_intercon
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/cpu/M_AXI" } [get_bd_intf_pins axi_intercon/S00_AXI]
validate_bd_design
save_bd_design
get_property IS_EVALUATION [get_ips <inst_name>]
Warning: Evaluation IPs produce bitstreams that expire after a few hours of hardware operation.