菜单
Analyze and reduce FPGA power consumption. Use when asked to measure power, run power optimization, reduce dynamic power, annotate switching activity, or audit clock and I/O power.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.
| name | vivado-power |
| version | 1.0.0 |
| description | Analyze and reduce FPGA power consumption. Use when asked to measure power, run power optimization, reduce dynamic power, annotate switching activity, or audit clock and I/O power. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"⚡"}} |
report_power -advisory -format text -file /tmp/vivaclaw_rpt/power.rpt
Extract key components:
grep -E "Total On-Chip|Dynamic|Static|Clocks |Signals |Logic |BRAM |DSP |I/O " /tmp/vivaclaw_rpt/power.rpt
| Component | Threshold | Action if Exceeded |
|---|---|---|
| Clocks | >30% dynamic | BUFG audit, CE gating |
| I/O | >25% dynamic | Reduce drive strength, SLEW SLOW |
| BRAM | >20% dynamic | Enable gating, output registers |
Read switching activity from simulation for accurate power:
read_saif simulation.saif -instance <top_instance>
report_power -file /tmp/vivaclaw_rpt/power_annotated.rpt
power_opt_design
Typically run post-place, pre-route. Inserts clock enables to reduce toggle rate on idle logic.
set_property SLEW SLOW [get_ports {data[*]}], set_property DRIVE 4 [get_ports {data[*]}]EN pins are not tied high if the block has idle cycles.