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Choose and run optimal synthesis strategy. Use when synthesizing a design, selecting synth directives, auditing BRAM/DSP/LUT inference quality, or improving synthesis QoR.
用 Codex 或 Claude 帮你安装 复制这段 Prompt，粘贴到 Codex、Claude 或其他助手里，让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
| name | vivado-synth |
| version | 1.0.0 |
| description | Choose and run optimal synthesis strategy. Use when synthesizing a design, selecting synth directives, auditing BRAM/DSP/LUT inference quality, or improving synthesis QoR. |
| metadata | {"openclaw":{"requires":{"bins":["vivado"]},"emoji":"⚙️"}} |
| Profile | Directive | Key Flags |
|---|---|---|
| Balanced | Default | -flatten_hierarchy rebuilt |
| High Perf | PerformanceOptimized | -retiming -flatten_hierarchy full |
| Area | AreaOptimized_high | -resource_sharing on -no_lc |
| Fast Iter | RuntimeOptimized | — |
synth_design -top <top> -part <part> -directive <dir> -flatten_hierarchy <mode> -fsm_extraction auto -retiming -resource_sharing <on/off>
report_utilization -hierarchical -file /tmp/vivaclaw_rpt/synth_util.rptreport_ram_utilization -file /tmp/vivaclaw_rpt/synth_ram.rpt
(* ram_style = "block" *) for large arrays.report_dsp_utilization -file /tmp/vivaclaw_rpt/synth_dsp.rpt
synth.log for encoding (one-hot vs sequential).report_design_analysis -complexity -logic_level_distribution -file /tmp/vivaclaw_rpt/synth_complexity.rpt
Identify Rent Exponent (>0.85 indicates placement congestion risks).
Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.
Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.
Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.
Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.
Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.
Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.