一键导入
arch-lookup
Look up Tensix architecture, instruction, or LLK implementation details across architectures. Orchestrates sage agents in parallel.
用 Codex 或 Claude 帮你安装 复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它检查 Skill 页面并帮你完成安装。
菜单
Look up Tensix architecture, instruction, or LLK implementation details across architectures. Orchestrates sage agents in parallel.
用 Codex 或 Claude 帮你安装 复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
| name | arch-lookup |
| description | Look up Tensix architecture, instruction, or LLK implementation details across architectures. Orchestrates sage agents in parallel. |
| user_invocable | true |
/arch-lookup "How does SFPMAD work?"
/arch-lookup "How does unpack handle Float16 on Blackhole?"
/arch-lookup "What is BroadcastType?"
/arch-lookup "How do T0/T1/T2 synchronize?"
Determine which architectures are relevant:
Before writing the sage prompt, classify the question. This determines which source the sage must consult first — otherwise the sage will default to grep and miss authoritative HW information.
| Question Type | Examples | Required Primary Source |
|---|---|---|
| HW capability / spec | "What formats does X support?", "What SFPU instructions exist?", "How wide is the FPU?", "How many DEST rows?" | Confluence (QSR) / DeepWiki (WH,BH) FIRST, code second |
| HW behavior / semantics | "How does SFPMAD handle NaN?", "When does the pipeline stall?", "What does instruction X do in HW?" | Confluence / DeepWiki FIRST, code second |
| LLK implementation | "How is matmul implemented?", "What does llk_unpack_AB do?", "Where is X wired up?" | Code FIRST (tt_llk_*/), docs second |
| Mixed / end-to-end | "How is Float16 handled from unpack to pack?" | Both required — docs for HW limits, code for the software path |
Critical distinction: LLK code shows what is wired up in software. It can lag or diverge from what the hardware actually supports. For HW-capability / HW-behavior questions, a grep-only answer is incomplete — the authoritative source is Confluence (Quasar) or DeepWiki / tt-isa-documentation (WH, BH).
Launch up to 3 agents IN PARALLEL using the Agent tool:
| Agent | Scope | Primary ISA Source |
|---|---|---|
sage-wormhole | tt_llk_wormhole_b0/ | DeepWiki + assembly.yaml |
sage-blackhole | tt_llk_blackhole/ | DeepWiki + assembly.yaml |
sage-quasar | tt_llk_quasar/ | Confluence + assembly.yaml (NO DeepWiki) |
Prompt construction rules:
"This is a HW-capability question. Consult Confluence first (sage-quasar) / DeepWiki tt-isa-documentation first (sage-wormhole, sage-blackhole) to get the authoritative HW answer. Use code grep only to cross-verify what is actually wired up in the LLK. If docs and code disagree, call out the conflict — do not silently prefer one."
After all sages return:
Before responding, verify:
Create, extend, debug, and validate Quasar LLK performance tests and their PerfRunType kernel paths. Use when adding perf_[op]_quasar.py, wiring PerfConfig, implementing UNPACK_ISOLATE / MATH_ISOLATE / PACK_ISOLATE / L1_CONGESTION, or investigating implausible Quasar perf metrics and dvalid handshakes.
Create, extend, debug, and validate Quasar LLK performance tests and their PerfRunType kernel paths. Use when adding perf_[op]_quasar.py, wiring PerfConfig, implementing UNPACK_ISOLATE / MATH_ISOLATE / PACK_ISOLATE / L1_CONGESTION, or investigating implausible Quasar perf metrics and dvalid handshakes.
Route gh-aw workflow design/create/debug/upgrade requests to the right prompts.
Convert LLK lib/API tile-size args to ckernel::TensorShape and maintain TRISC TensorShape coverage. Use when adding TensorShape parameters, replacing face_r_dim/num_faces, editing LLK_VALIDATE_TENSOR_SHAPE_*, regenerating tensor_shape_coverage_*.h, or reviewing TensorShape PRs.
Audit LLK code for races on the backend CONFIG register file where differently-named fields share the SAME 32-bit config word — both cross-thread (unpack/math/pack write the same word) and intra-thread (a full-word write clobbers a sibling field the same thread set elsewhere). Use after adding/changing any ALU_FORMAT_SPEC / ALU_ACC_CTRL / ALU_ROUNDING_MODE / STACC_RELU / THCON_SEC* write, any WRCFG_32b/cfg[]= full-word write to a multi-field word, or any cfg_reg_rmw_tensix on a word another thread also touches.
Audit hand-written Tensix/SFPU instruction sequences for missing pipeline-latency padding — where a dependent instruction consumes a multi-cycle-latency result before it is ready and a NOP (or independent-instruction spacing) is required. Use after touching any raw TTI_SFP*/TTI_* sequence, ckernel_sfpu_* kernels, or hand-assembled instruction streams. NOT a cross-thread race — an intra-thread micro-architectural hazard.