Read-only architecture review of RTL vs uArch spec with area/timing/power tradeoffs. Use for post-RTL architecture sign-off or suspected spec mismatch.
Builds Phase 3 SystemC TLM-2.0 bus functional models with AMBA (AXI/AHB/APB) support. Use for 'develop BFM', 'SystemC TLM model', 'bus functional model'.
Encoder RD evaluation of C ref model: BD-PSNR/BD-rate (VCEG-M33) across sequences/QPs — 'RD eval', 'BD-rate', codec algorithm quality comparison.
Validate spec contracts across phase boundaries (P3 uarch to P4 RTL to P5 verify): port widths, memory class, REQ traceability. Use at P4/P5 entry.
Internal reference: p1 spec research policy (agent-loaded; do not invoke).
Full 6-phase RTL pipeline from spec to verified design (P1 research through P6 design note). Triggers: 'design a chip', 'full pipeline', 'autopilot'.
Initialize RTL project workspace: directory structure, coding rules, phase guides. Run once per project. Triggers: 'init project', 'new project'.
Plugin diagnostics: version, EDA tool status, state files, hook health. Triggers: 'rat debug', 'plugin status', troubleshooting plugin behavior.