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chip-low-power-architect

Use when designing low-power architecture for chip modules. Triggers on '低功耗', 'UPF', '功耗域', 'power domain', 'isolation', 'retention', 'clock gating', 'power gating'. Designs power domain partitioning, isolation/retention strategy and UPF.

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Repository
zhaixin244-wq/fnw
Last source activity
May 18, 2026 at 08:25
Detected SKILL.md language
Chinese
Stars
27
Forks
9

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