behavioral-veriloga-eval

Use when visible/public EVAS simulation is allowed for a Verilog-A voltage-domain model. Covers when EVAS applies, how to run evas-sim, minimal Spectre .scs syntax, save/output files, and common EVAS setup failures. Does not teach Verilog-A authoring.

Use when writing, fixing, or reviewing Verilog-A behavioral modules. Focuses on syntax, module/port discipline, state/event modeling, transition outputs, vector handling, and EVAS/Spectre portability. Does not provide circuit-specific recipes or simulation workflow.