londey

Spawn a four-person GPU development team with coordinator, verilog specialist, rust digital twin specialist, and verification specialist. Use when a task benefits from parallel RTL + twin + verification work.

Component boundaries, interfaces, bound SVA properties, and conformance-harness discipline for SystemVerilog projects

Verilog/SystemVerilog coding style and Verilator workflow guidance

Guide for Rust development including code style, testing, building, and quality checks using cargo tools. Apply when working with Rust code, Cargo.toml, or running cargo commands.

Use this skill whenever writing, reviewing, or debugging SystemVerilog for Lattice ECP5 FPGAs that must be compatible with both Yosys (nextpnr synthesis) and Verilator (simulation). Covers ECP5-specific primitives (EHXPLLL, DP16KD, PDPW16KD, MULT18X18D, ALU54B, DCCA, ODDRX1F, OSCG, JTAGG, USRMCLK, GSR, etc.), correct explicit instantiation patterns, Verilator stub strategies, macro guards, resource budgeting for ECP5-25K, and common pitfalls. Trigger on any mention of ECP5, nextpnr, Yosys synthesis with Verilator cosim, FPGA primitives in SV, DSP multipliers, block RAM configurations, or questions about making vendor hard IP simulate correctly. Use when the user asks about block RAM aspect ratios, DSP pipeline registers, dual/single-port RAM configs, or wants to explicitly instantiate limited hard resources rather than relying on inference.

C++20 coding guidelines and conventions. Use when writing, reviewing, or refactoring C++ code. Covers naming, formatting, resource management, type safety, modern C++20 features, and design principles from the C++ Core Guidelines and Sean Parent's Better Code series.