Ejecuta cualquier Skill en Manus
con un clic

Ejecuta cualquier Skill en Manus con un clic

vivado-timing

Estrellas3

Forks0

Actualizado22 de abril de 2026 a las 23:03

Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.

Instalación

Instalar con Codex o Claude Copia este prompt, pégalo en Codex, Claude u otro asistente, y deja que revise la página de la skill y la instale por ti.

Ejecutar en Manus

Fuente

devansh0703

devansh0703/vivaclaw-agent

Abrir repositorio de GitHub Ver repositorios del creador

Descarga

Ejecutar en Manus

Ocupaciones relacionadasSOC

Basado en la clasificación ocupacional SOC

Desarrolladores de softwareOcupaciones informáticas y matemáticas·SOC 15-1252

SKILL.md

readonly

name	vivado-timing
version	1.0.0
description	Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"⏱️"}}

Vivado Timing Closure Runbook

1. Diagnostic Suite

open_checkpoint /tmp/vivaclaw_post_route.dcp
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_internal -max_paths 10 -input_pins -file /tmp/vivaclaw_rpt/timing_summary.rpt
report_design_analysis -timing -logic_level_distribution -file /tmp/vivaclaw_rpt/design_analysis.rpt

2. Path Investigation

set p [get_timing_paths -max_paths 1 -slack_lesser_than 0 -delay_type max]
if {$p != ""} {
    puts "SLACK: [get_property SLACK $p]"
    puts "LOGIC_LEVELS: [get_property LOGIC_LEVELS $p]"
    puts "DATAPATH_DELAY: [get_property DATAPATH_DELAY $p]"
}

3. Strategy Table

Condition	Action
Logic Levels > 8	Re-synth: `-directive PerformanceOptimized -retiming`
Route Delay > 60%	`route_design -directive AggressiveExplore`
Hold Violation	`phys_opt_design -directive ExploreWithHoldFix`
High Fanout (>5k)	`set_property MAX_FANOUT 100 [get_cells <driver>]`

4. Logic Level Targets (MHz vs Levels)

MHz	Max Levels
100	16
200	8
300	6
400	4

5. Directive Escalation Ladder

place=WLDrivenPlacement, route=Default
place=AltSpreadLogic_high, route=Explore
place=ExtraNetDelay_high, route=AggressiveExplore
phys_opt=AggressiveExplore, route=MoreGlobalIterations
phys_opt=AlternativeFlowWithRetiming, route=AggressiveExplore

Más de este repositorio

mismo repositorio

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado FPGA design flow from RTL sources to bitstream. Use when asked to synthesize, implement, build, or compile an FPGA design. Also handles project creation, checkpoint management, and run orchestration.

2026-04-223

vivado-cdc

devansh0703/vivaclaw-agent

Analyze and fix clock domain crossing violations. Use when CDC violations appear, when auditing multi-clock designs, or when reviewing set_false_path and set_max_delay exceptions for safety.

2026-04-223

vivado-constraints

devansh0703/vivaclaw-agent

Author and audit Vivado XDC constraint files. Use when creating constraints, finding unconstrained paths, debugging timing exceptions, checking clock definitions, or auditing I/O delays for completeness.

2026-04-223

vivado-debug

devansh0703/vivaclaw-agent

Insert ILA and VIO debug cores into a Vivado design. Use when asked to add hardware debug probes, set up ILA trigger conditions, insert VIO for stimulus injection, or generate .ltx probeinfo files.

2026-04-223

vivado-floorplan

devansh0703/vivaclaw-agent

Create Pblock floorplan constraints in Vivado. Use when dealing with placement congestion, SSI multi-die devices, reconfigurable partitions (DFX), or when critical paths need physical locality.

2026-04-223

vivado-flow

devansh0703/vivaclaw-agent

Run a complete Vivado design flow: project creation, synthesis, implementation, bitstream. Use when asked to build, synthesize, implement, or compile an FPGA design from RTL sources.

2026-04-223

name	vivado-timing
version	1.0.0
description	Analyze and fix timing violations. Use when WNS is negative, when asked to close timing, fix setup/hold violations, analyze critical paths, or improve max frequency.
metadata	{"openclaw":{"requires":{"bins":["vivado"]},"emoji":"⏱️"}}

Vivado Timing Closure Runbook

1. Diagnostic Suite

open_checkpoint /tmp/vivaclaw_post_route.dcp
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_internal -max_paths 10 -input_pins -file /tmp/vivaclaw_rpt/timing_summary.rpt
report_design_analysis -timing -logic_level_distribution -file /tmp/vivaclaw_rpt/design_analysis.rpt

2. Path Investigation

set p [get_timing_paths -max_paths 1 -slack_lesser_than 0 -delay_type max]
if {$p != ""} {
    puts "SLACK: [get_property SLACK $p]"
    puts "LOGIC_LEVELS: [get_property LOGIC_LEVELS $p]"
    puts "DATAPATH_DELAY: [get_property DATAPATH_DELAY $p]"
}

3. Strategy Table

Condition	Action
Logic Levels > 8	Re-synth: `-directive PerformanceOptimized -retiming`
Route Delay > 60%	`route_design -directive AggressiveExplore`
Hold Violation	`phys_opt_design -directive ExploreWithHoldFix`
High Fanout (>5k)	`set_property MAX_FANOUT 100 [get_cells <driver>]`

4. Logic Level Targets (MHz vs Levels)

MHz	Max Levels
100	16
200	8
300	6
400	4

5. Directive Escalation Ladder

place=WLDrivenPlacement, route=Default
place=AltSpreadLogic_high, route=Explore
place=ExtraNetDelay_high, route=AggressiveExplore
phys_opt=AggressiveExplore, route=MoreGlobalIterations
phys_opt=AlternativeFlowWithRetiming, route=AggressiveExplore