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Arquitetura e Engenharia · Habilidades e competências profissionais · SOC 17-2131 · 164 skills

Contexto da ocupação

Estas tarefas do O*NET descrevem a ocupação e contextualizam o mapeamento SOC; não significam que cada Skill listado execute todas as tarefas.

  • Analyze product failure data and laboratory test results to determine causes of problems and develop solutions.
  • Design and direct the testing or control of processing procedures.
  • Monitor material performance, and evaluate its deterioration.

As tarefas do O*NET são exibidas no idioma de origem (inglês). Os dados de tarefas foram extraídos do O*NET® 29.1 Database da USDOL/ETA e são usados sob CC BY 4.0.

Fontes representativas

Uma amostra limitada de Skills populares mapeados para esta ocupação, com no máximo um Skill por repositório do GitHub. A lista completa aparece a seguir.

semiconductor-process-master
127
swaylqswaylq/master-skill
半导体芯片制造工艺 (Semiconductor Process Engineering / 半导体芯片制造工艺 — 以「物理化学极限 + 良率经济双重约束」为特征的集成电路前道/后道制造工艺认知操作系统:从「器件架构与微缩路线(planar→FinFET→GAA nanosheet→CFET、等效微缩 DTCO/STCO、背面供电 BSPDN)→ 工艺整合(FEOL/MOL/BEOL 模块协同、PDK、流片 tape-out)→ 单元工艺(光刻 litho(DUV 浸没式 193i / EUV 13.5nm / 多重曝光 SADP-SAQP / OPC / mask)、刻蚀 etch(RIE/ICP/原子层刻蚀 ALE)、薄膜沉积 depo(CVD/PECVD/LPCVD/ALD/PVD/外延 epi/电镀 Cu)、掺杂 doping(离子注入 ion implant / 退火 RTA-laser anneal)、CMP 化学机械抛光、清洗 cleaning)→ 量测检测 metrology(CD-SEM / OCD / overlay / 椭偏 ellipsometry / 缺陷检测 defect inspection / e-beam)→ 良率工程 yield(缺陷密度 / SPC 统计过程控制 / FDC / APC / DOE 实验设计 / 良率爬坡 yield ramp)→ 先进封装 advanced packaging(2.5D/3D、CoWoS、HBM、混合键合 hybrid bonding、chiplet、TSV)」的完整器件-工艺-良率-量产决策链。覆盖 (a) 第一性张力 — **物理/化学/材料的硬约束(量子隧穿、短沟道效应、RC 延迟、热预算、缺陷物理、ppb 级污染控制)⇄ 良率/成本/产能的经济约束(每片晶圆成本、良率是主经济指标、D0 缺陷密度、wafer-per-hour、折旧)**;**持续微缩/摩尔定律(dimensional + equivalent scaling、节点路线图 N5/N3/N2/A16/A14、high-NA EUV)⇄ 物理极限/微缩放缓(原子尺度、漏电、功耗墙、成本墙、'摩尔定律已死'之争)**;**协同优化/整合(DTCO 设计-工艺协同、STCO 系统-工艺协同、模块间 trade-off)⇄ 单模块极致优化(单一 unit process 工艺窗

Todos os Skills mapeados

Explore o mapeamento completo por popularidade do repositório ou atividade recente da fonte.

Os nomes e as descrições dos Skills permanecem no idioma fornecido pelo repositório de origem.

Ordenar por
semiconductor-process-master
127
swaylqswaylq/master-skill
半导体芯片制造工艺 (Semiconductor Process Engineering / 半导体芯片制造工艺 — 以「物理化学极限 + 良率经济双重约束」为特征的集成电路前道/后道制造工艺认知操作系统:从「器件架构与微缩路线(planar→FinFET→GAA nanosheet→CFET、等效微缩 DTCO/STCO、背面供电 BSPDN)→ 工艺整合(FEOL/MOL/BEOL 模块协同、PDK、流片 tape-out)→ 单元工艺(光刻 litho(DUV 浸没式 193i / EUV 13.5nm / 多重曝光 SADP-SAQP / OPC / mask)、刻蚀 etch(RIE/ICP/原子层刻蚀 ALE)、薄膜沉积 depo(CVD/PECVD/LPCVD/ALD/PVD/外延 epi/电镀 Cu)、掺杂 doping(离子注入 ion implant / 退火 RTA-laser anneal)、CMP 化学机械抛光、清洗 cleaning)→ 量测检测 metrology(CD-SEM / OCD / overlay / 椭偏 ellipsometry / 缺陷检测 defect inspection / e-beam)→ 良率工程 yield(缺陷密度 / SPC 统计过程控制 / FDC / APC / DOE 实验设计 / 良率爬坡 yield ramp)→ 先进封装 advanced packaging(2.5D/3D、CoWoS、HBM、混合键合 hybrid bonding、chiplet、TSV)」的完整器件-工艺-良率-量产决策链。覆盖 (a) 第一性张力 — **物理/化学/材料的硬约束(量子隧穿、短沟道效应、RC 延迟、热预算、缺陷物理、ppb 级污染控制)⇄ 良率/成本/产能的经济约束(每片晶圆成本、良率是主经济指标、D0 缺陷密度、wafer-per-hour、折旧)**;**持续微缩/摩尔定律(dimensional + equivalent scaling、节点路线图 N5/N3/N2/A16/A14、high-NA EUV)⇄ 物理极限/微缩放缓(原子尺度、漏电、功耗墙、成本墙、'摩尔定律已死'之争)**;**协同优化/整合(DTCO 设计-工艺协同、STCO 系统-工艺协同、模块间 trade-off)⇄ 单模块极致优化(单一 unit process 工艺窗

Agora são exibidos 12 Skills.