一键导入
sim-tool-profiles
Internal reference: sim tool profiles (agent-loaded; do not invoke).
用 Codex 或 Claude 帮你安装 复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它检查 Skill 页面并帮你完成安装。
菜单
Internal reference: sim tool profiles (agent-loaded; do not invoke).
用 Codex 或 Claude 帮你安装 复制这段 Prompt,粘贴到 Codex、Claude 或其他助手里,让它检查 Skill 页面并帮你完成安装。
基于 SOC 职业分类
Read-only architecture review of RTL vs uArch spec with area/timing/power tradeoffs. Use for post-RTL architecture sign-off or suspected spec mismatch.
Builds Phase 3 SystemC TLM-2.0 bus functional models with AMBA (AXI/AHB/APB) support. Use for 'develop BFM', 'SystemC TLM model', 'bus functional model'.
Encoder RD evaluation of C ref model: BD-PSNR/BD-rate (VCEG-M33) across sequences/QPs — 'RD eval', 'BD-rate', codec algorithm quality comparison.
Validate spec contracts across phase boundaries (P3 uarch to P4 RTL to P5 verify): port widths, memory class, REQ traceability. Use at P4/P5 entry.
Internal reference: p1 spec research policy (agent-loaded; do not invoke).
Full 6-phase RTL pipeline from spec to verified design (P1 research through P6 design note). Triggers: 'design a chip', 'full pipeline', 'autopilot'.
| name | sim-tool-profiles |
| description | Internal reference: sim tool profiles (agent-loaded; do not invoke). |
| user-invocable | false |
scripts/run_sim.shverilator:
scripts/run_sim.sh --sim verilator --top <tb_top> -f rtl/filelist_top.f --outdir sim/reports --traceiverilog:
scripts/run_sim.sh --sim iverilog --top <tb_top> -f rtl/filelist_top.f --outdir sim/reportsvcs:
scripts/run_sim.sh --sim vcs --top <tb_top> -f rtl/filelist_top.f --outdir sim/reportsxrun:
scripts/run_sim.sh --sim xrun --top <tb_top> -f rtl/filelist_top.f --outdir sim/reportsquesta:
scripts/run_sim.sh --sim questa --top <tb_top> -f rtl/filelist_top.f --outdir sim/reportsCode coverage must be enabled at both compile and runtime for all commercial simulators.
| Simulator | Compile Flag | Runtime Flag | Coverage DB | Merge Tool |
|---|---|---|---|---|
| VCS | -cm line+cond+fsm+tgl+branch | -cm line+cond+fsm+tgl+branch -cm_dir <dir>.vdb | .vdb directory | urg -dir *.vdb -format both |
| Xcelium | -coverage all | -coverage all -covworkdir <dir>/cov_work -covscope tb_top | cov_work/ directory | imc -exec merge.tcl |
| Questa | +cover=bcestf (at vlog) | -coverage (at vsim) + -do "coverage save -onexit <file>.ucdb" | .ucdb file | vcover merge out.ucdb *.ucdb |
Questa gotcha: +cover=bcestf at vlog compile is mandatory — runtime -coverage alone collects nothing.
UVM regression runner: {plugin_root}/skills/rtl-p5s-uvm-verify/scripts/run_regression_uvm.sh ({plugin_root} = plugin root from .rat/state/spawn-context.json)
toolstatus (pass or fail)errors_countwarnings_countlog_pathreplay_path