gf-synth
Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40"
来源信息
- 仓库
- codejunkie99/Gateflow-Plugin
- 最近来源活动
- 2026年3月26日 10:52
- 检测到的 SKILL.md 语言
- 英语
- 星标
- 117
- 分支
- 16
安装方式
默认使用会先检查来源的 Prompt；你也可以切换为直接命令，或下载本地副本。
检查来源文件
决定是否安装前，请先阅读 SKILL.md，以及 SkillsMP 当前展示的配套文件。
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SKILL.md
来源说明 · 只读预览- name
- gf-synth
- description
- Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40"
- allowed-tools
- ["Bash","Read","Write","Glob","Grep","Task"]
# GF-Synth — Yosys Synthesis Skill
## Tool Detection
```bash
which yosys
```
If not found:
```
---GATEFLOW-RESULT---
STATUS: ERROR
DETAILS: Yosys not installed. Install to enable synthesis.
macOS: brew install yosys
Linux: sudo apt install yosys
---END-GATEFLOW-RESULT---
```
## Pre-Synthesis SV Subset Check
Before synthesis, scan for unsupported constructs:
```bash
grep -rn "^\s*interface\s\|^\s*modport\s\|^\s*class\s\|^\s*bind\s" <files>
```
If found, warn user. Do NOT proceed — it will produce confusing errors.
## Workflow
1. Check project context (`.gateflow/project.yaml`) for target
2. Pre-synthesis lint for unsupported SV constructs
3. Map board to Yosys synth target
4. Run synthesis via sv-synth agent or directly
5. Parse stat output for LUT/FF/BRAM/DSP
6. Report structured result
## Result Format
```
---GATEFLOW-RESULT---
STATUS: PASS | FAIL | ERROR
RESOURCES:
LUTs: N
FFs: N
BRAM: N
DSP: N
TARGET: ice40 | ecp5 | gowin | xilinx | generic
FILES: [synth output files]
DETAILS: [summary or error explanation]
---END-GATEFLOW-RESULT---
```
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