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codejunkie99
GitHub creator profile

codejunkie99

Repository-level view of 97 collected skills across 11 GitHub repositories.

skills collected
97
repositories
11
updated
Aug 18, 2026
Showing the top 8 repositories here; full repository list continues below.
repository explorer

Repositories and representative skills

apology-crafter
writers-and-authors

Use when the user wants to craft a sincere, accountable apology in both written and spoken versions, without deflection. Triggers include "draft an apology", "how should I apologize", "say sorry to".

Apr 26, 2026
difficult-conversation-prep
human-resources-specialists

Use when the user wants to prepare for a hard conversation with empathetic-but-direct opening, defensiveness handling, and resolution paths. Triggers include "difficult conversation", "hard talk", "tough conversation prep".

Apr 26, 2026
elevator-pitch-builder
writers-and-authors

Use when the user wants three energy-level variants of an elevator pitch (bold, conversational, data-driven). Triggers include "elevator pitch", "pitch this product", "30 second pitch".

Apr 26, 2026
feedback-giver
human-resources-managers-113121general-and-operations-managers-111021

Use when the user wants to draft spoken feedback using observation/impact/expectation/support framework. Triggers include "give feedback", "feedback to my report", "performance feedback".

Apr 26, 2026
presentation-outliner
writers-and-authors

Use when the user wants a tight presentation outline with hook, problem, solution, evidence, objection handling, and clear CTA. Triggers include "outline a presentation", "talk outline", "structure my pitch deck".

Apr 26, 2026
data-interpreter
data-scientists-152051

Use when the user wants plain-English interpretation of a dataset including patterns, surprises, and misleading aspects. Triggers include "analyze this data", "interpret these numbers", "what does this data mean".

Apr 26, 2026
research-synthesizer
social-scientists-and-related-workers-all-other

Use when the user has multiple research sources on a topic and wants genuine synthesis of themes, contradictions, and gaps — not separate summaries. Triggers include "synthesize this research", "compare these sources", "research synthesis".

Apr 26, 2026
survey-analyzer
market-research-analysts-and-marketing-specialists-131161

Use when the user wants to analyze survey results for findings, consensus, division, surprises, and actionable recommendations. Triggers include "analyze survey", "survey results", "what does this survey show".

Apr 26, 2026
Showing 8 of 40 collected skills.
gf-tui
software-developers

GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.

May 21, 2026
gf-release
software-developers

GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.

May 20, 2026
gf-fusesoc
electronics-engineers-except-computer

FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL…

Apr 15, 2026
gf-learn
postsecondary-teachers-all-other

SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.

Apr 15, 2026
gf-router
electronics-engineers-except-computer

Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.

Apr 15, 2026
gf
electronics-engineers-except-computer

Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital…

Apr 15, 2026
gf-summary
electronics-engineers-except-computer

Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.

Apr 15, 2026
gf-architect
electronics-engineers-except-computer

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase",…

Apr 11, 2026
Showing 8 of 27 collected skills.
gateflow-behavior
software-developers

This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring…

Feb 5, 2026
systemverilog-rtl-design
software-developers

Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register…

Feb 5, 2026
systemverilog-lint-fixing
software-developers

This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal', 'fix warnings', 'Verilator error', 'WIDTHTRUNC', 'BLKSEQ', or asks to 'check my code' or 'find errors'. Provides error-specific fix patterns…

Feb 5, 2026
systemverilog-testbench-patterns
software-quality-assurance-analysts-and-testers

This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create test stimulus', 'verify the design', 'add clock generation', or 'write a self-checking test'. Provides testbench templates, clock/reset…

Feb 5, 2026
systemverilog-verification
software-quality-assurance-analysts-and-testers

Provides verification methodology, SVA assertion patterns, coverage techniques, and testbench templates. Use when the user mentions 'testbench', 'assertion', 'SVA', 'property', 'sequence', 'coverage', 'covergroup', 'coverpoint', 'bins', 'cross coverage',…

Feb 5, 2026
vcd-waveform-analysis
software-developers

This skill should be used when the user mentions 'waveform', 'VCD file', 'simulation results', 'signal trace', 'debug the output', 'what happened in sim', 'show me the waves', or 'analyze timing'. Provides VCD parsing, clock detection, anomaly identification,…

Feb 5, 2026
systemverilog-development
software-developers

This skill should be used when the user asks to 'design a module', 'write SystemVerilog', 'implement an FSM', 'create a pipeline', or works with .sv/.svh/.v/.vh files. Provides modern SV conventions, coding patterns, and synthesizability guidance.

Feb 5, 2026
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