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codejunkie99
Profil créateur GitHub

codejunkie99

Vue par dépôt de 97 skills collectés dans 11 dépôts GitHub.

skills collectés
97
dépôts
11
mis à jour
18 août 2026
Les 8 principaux dépôts sont affichés ici ; la liste complète continue ci-dessous.
explorateur de dépôts

Dépôts et skills représentatifs

apology-crafter
Écrivains et auteurs

Use when the user wants to craft a sincere, accountable apology in both written and spoken versions, without deflection. Triggers include "draft an apology", "how should I apologize", "say sorry to".

26 avr. 2026
difficult-conversation-prep
Spécialistes en ressources humaines

Use when the user wants to prepare for a hard conversation with empathetic-but-direct opening, defensiveness handling, and resolution paths. Triggers include "difficult conversation", "hard talk", "tough conversation prep".

26 avr. 2026
elevator-pitch-builder
Écrivains et auteurs

Use when the user wants three energy-level variants of an elevator pitch (bold, conversational, data-driven). Triggers include "elevator pitch", "pitch this product", "30 second pitch".

26 avr. 2026
feedback-giver
Responsables des ressources humainesDirecteurs généraux et responsables des opérations

Use when the user wants to draft spoken feedback using observation/impact/expectation/support framework. Triggers include "give feedback", "feedback to my report", "performance feedback".

26 avr. 2026
presentation-outliner
Écrivains et auteurs

Use when the user wants a tight presentation outline with hook, problem, solution, evidence, objection handling, and clear CTA. Triggers include "outline a presentation", "talk outline", "structure my pitch deck".

26 avr. 2026
data-interpreter
Scientifiques des données

Use when the user wants plain-English interpretation of a dataset including patterns, surprises, and misleading aspects. Triggers include "analyze this data", "interpret these numbers", "what does this data mean".

26 avr. 2026
research-synthesizer
Scientifiques sociaux et travailleurs connexes, autres

Use when the user has multiple research sources on a topic and wants genuine synthesis of themes, contradictions, and gaps — not separate summaries. Triggers include "synthesize this research", "compare these sources", "research synthesis".

26 avr. 2026
survey-analyzer
Analystes en études de marché et spécialistes en marketing

Use when the user wants to analyze survey results for findings, consensus, division, surprises, and actionable recommendations. Triggers include "analyze survey", "survey results", "what does this survey show".

26 avr. 2026
Affichage de 8 skills collectés sur 40.
gf-tui
Développeurs de logiciels

GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface.

21 mai 2026
gf-release
Développeurs de logiciels

GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.

20 mai 2026
gf-fusesoc
Ingénieurs électroniques (sauf informatique)

FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL…

15 avr. 2026
gf-learn
Enseignants postsecondaires, autres

SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.

15 avr. 2026
gf-router
Ingénieurs électroniques (sauf informatique)

Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.

15 avr. 2026
gf
Ingénieurs électroniques (sauf informatique)

Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital…

15 avr. 2026
gf-summary
Ingénieurs électroniques (sauf informatique)

Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.

15 avr. 2026
gf-architect
Ingénieurs électroniques (sauf informatique)

Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase",…

11 avr. 2026
Affichage de 8 skills collectés sur 27.
gateflow-behavior
Développeurs de logiciels

This skill should be used when the user is working on any SystemVerilog, Verilog, HDL, RTL, FPGA, or ASIC development task. Provides behavioral rules for GateFlow: auto-chain workflows, context-aware actions, and seamless tool execution without requiring…

5 févr. 2026
systemverilog-rtl-design
Développeurs de logiciels

Provides RTL design patterns, synthesis guidelines, and coding templates. Use when the user mentions 'module design', 'FSM', 'state machine', 'pipeline', 'synthesizable', 'parameterize', 'parameter', 'localparam', 'clock domain', 'CDC', 'FIFO', 'register…

5 févr. 2026
systemverilog-lint-fixing
Développeurs de logiciels

This skill should be used when the user mentions 'lint error', 'width mismatch', 'inferred latch', 'undriven signal', 'fix warnings', 'Verilator error', 'WIDTHTRUNC', 'BLKSEQ', or asks to 'check my code' or 'find errors'. Provides error-specific fix patterns…

5 févr. 2026
systemverilog-testbench-patterns
Analystes en assurance qualité des logiciels et testeurs

This skill should be used when the user asks to 'write a testbench', 'test this module', 'add assertions', 'create test stimulus', 'verify the design', 'add clock generation', or 'write a self-checking test'. Provides testbench templates, clock/reset…

5 févr. 2026
systemverilog-verification
Analystes en assurance qualité des logiciels et testeurs

Provides verification methodology, SVA assertion patterns, coverage techniques, and testbench templates. Use when the user mentions 'testbench', 'assertion', 'SVA', 'property', 'sequence', 'coverage', 'covergroup', 'coverpoint', 'bins', 'cross coverage',…

5 févr. 2026
vcd-waveform-analysis
Développeurs de logiciels

This skill should be used when the user mentions 'waveform', 'VCD file', 'simulation results', 'signal trace', 'debug the output', 'what happened in sim', 'show me the waves', or 'analyze timing'. Provides VCD parsing, clock detection, anomaly identification,…

5 févr. 2026
systemverilog-development
Développeurs de logiciels

This skill should be used when the user asks to 'design a module', 'write SystemVerilog', 'implement an FSM', 'create a pipeline', or works with .sv/.svh/.v/.vh files. Provides modern SV conventions, coding patterns, and synthesizability guidance.

5 févr. 2026
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