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RTL-CLAW
RTL-CLAW contains 5 collected skills from TONGJI-EDA-LAB, with repository-level occupation coverage and site-owned skill detail pages.
skills collected
5
Stars
59
updated
2026-03-25
Forks
11
Occupation coverage
1 occupation categories · 100% classified
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Skills in this repository
creator/repo/skill
skill
occupation
description
updated
rtl-spec-analyzer
electronics-engineers-except-computer
分析RTL Design和Specification，提取功能点并完成Signal到Pin的映射分析
2026-03-25
testbench-generator
electronics-engineers-except-computer
基于RTL-Spec分析结果，生成包含激励序列和参考模型的完整SystemVerilog Testbench
2026-03-25
verilog-merge
electronics-engineers-except-computer
将拆分后的Verilog子模块合并回完整RTL，并用testbench-generator+iverilog完成最终验证
2026-03-25
verilog-optimization
electronics-engineers-except-computer
在 Verilog partition 之后、merge 之前对 part 文件做 Yosys 优化，并用 Verible 进行语法/lint 兜底
2026-03-25
verilog-partition
electronics-engineers-except-computer
利用LLM Agent自动对Verilog RTL设计进行拆分，按always块生成多个子模块
2026-03-25